Test Pattern Generation Using Lfsr with Reseeding Scheme for Bist Designs

TEST PATTERN GENERATION USING LFSR WITH RESEEDING SCHEME FOR BIST DESIGNS Leeba Varghese, Suranya G Electronics and Communication Department/ MG University MG University/ Ilahia College of Engineering and Technology Ilahia College of Engineering and Technology Mulavoor P.O, Muvattupuzha Pin: 686673 Kerala India ______________________________________________________________________________________ Abstract: In this paper we present LFSR reseeding scheme for BIST. A time -to –market efficient algorithm is introduced for selecting reseeding points in the test sequence. This algorithm targets complete fault coverage and minimization of the test length. Functional broadside tests that avoid over testing by ensuring that a circuit traverses only reachable states during the functional clock cycles of a test[1]. These consist of the input vectors and the corresponding responses. They check for proper operation of a verified design by testing the internal chip nodes. Functional tests cover a very high percentage of modeled faults in logic circuits and their generation is the main topic of this paper. Function test sequence is generated by LFSR. Often, functional vectors are understood as verification vectors, which are used to verify whether the hardware actually matches its specification. However, in the ATE world, any vectors applied are understood to be functional fault coverage vectors applied during manufacturing test. This paper shows the on chip test Generation for a bench mark circuit using simple fixed hardware design with small no of parameters altered in the design for the generation of no of patterns. If the patterns of the input test vector results a fault simulation then circuit test is going to fail.